1. Field of the Invention
This invention relate to systems and circuits for the transmission of multiple digital data bits simultaneously on a single transmission medium between a transmitter and a receiver. More particularly this invention relates to a current mode multiple bit data bus to transmit and receive multiple digital data bits on a single transmission medium.
2. Description of Related Art
Typically, when two or more signals are routed in parallel over significant distances a data bus structure is often used. These distances may be on the order of from 1 mm to more than 20 mm of aluminum metalization on semiconductor chips, to as much as a meter of wiring pattern on a printed circuit card, to many meters of transmission line cabling to cover long distances. Often the data bus will contain two wires per signal transmission to have a differential signal to improve speed of the bus.
The important parameters or "figures of merit" for a data bus include: bandwidth of data transmission (bits per wire per second), power consumed (especially the AC power consumed by charging and discharging the data bus capacitances), and chip area consumed per bit versus the length of the distance of the transmission. There has been much discussion in the literature that the speed of the data bus, rather than the intrinsic CMOS gate speed, dominates chip performance beyond about 0.35 .mu.m technology. The reason that the transmission speed is the dominating factor is simply that the aluminum wires are getting narrower, and chips are simultaneously getting physically larger. So the total resistance of the wires is going up since the wires are becoming longer and narrower. In addition to the longer wire length the separation between metal lines is also getting smaller which further increases the capacitance between lines. The net change is that the wiring delay due to the resistive-capacitive delay is increasing. The above mentioned differential structure of bus allow smaller voltage swings and consequently fewer resistive-capacitive delays.
One known method for reducing wiring delays is to send the signal as a current rather than a voltage signal. In this case the voltage on the bus wire does not change drastically during the signal transition, but the current through the wire is modulated. Since the voltage is not changed, the resistive-capacitive delay is not a factor is the transmission time. The delay for the bus is now the inherent speed of light delay of the transmission medium, which will be much less than the resistive-capacitive delay. "Current Mode Techniques for High Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's" Seevinck et al., IEEE Journal of Solid State Circuits, Vol. 26, No. 4 April 1991, pp. 525-535 documents a simplified model with current mode propagation delays. An example of an application of these simplified models are shown in "A 1.6 Gb/s Data Rate 1 Gb Synchronous DRAM with Hierarchical Square Shaped Memory Block and Distributed Bank Architecture" Nitta et al., Proceedings of the International Solid State Circuits Conference, SP23.5, p 302, 1996.
In "1 Gb/s Current-Mode Bidirectional I/O Buffer", Sim et al., Symposium on VLSI Circuits Digest of Technical Papers, IEEE, 1997, a current mode bidirectional driver and receiver is disclosed. The circuit described is a simultaneous bidirectional buffer having low power consumption. The reduced voltage swing on the transmission line and low impedance node within the buffer allow for high bandwidth. The input and output circuits use current mode circuits to transfer the digital data across the transmission line.
U.S. Pat. No. 5,355,391 (Hororwitz et al.) describes a high speed bus system. The bus configuration places master devices at one end of an unterterminated transmission line and all slave devices distributed along the remaining length of the transmission line with the opposite end terminated. CMOS current mode drivers and receivers are implemented to allow low voltage swings on the transmission line.
U.S. Pat. No. 4,481,625 (Roberts et al.) describes a high speed data bus for communication between functional units of a very large computer system. The drivers and receivers that will allow communication between the functional units are operated in a current mode so that signal propagation on the bus encounters no significant discontinuity in line impedance when it passes an activated driver. Thus reflections are avoided and high speed bus "turn-around" is possible. The drivers and receivers are differential and the bus is configured as a "pseudo twisted pair" to even out any imbalances between line pairs.
U.S. Pat. No. 5,450,026 (Morano) describes a differential current mode bus driver that will couple input digital signals to a bus which is normally biased to one of the logic states. The bus driver will respond to a digital signal of the opposite logic state by connecting a current source to one lead of the bus and a current sink to the other lead of the bus. The bus is driven to a voltage level representing the opposite logic state. If the input is at the normally biased logic state, the driver disconnects the current source and sink from the bus and connects the current source and sink together. The bus remains biased to the first level.
U.S. Pat. No. 5,254,883 (Hororwitz et al.) discloses a current mode driver to transmit digital data to a bus. The current mode driver has transistor circuitry to control current on the bus and a variable level circuit that can adjust the current level on the bus. The user may adjust the level of the current on the bus.
The concept of using multiple signal levels to represent digital data is known in the art. The simultaneous bidirectional transmission of data on a bus as shown in Sim et al. is an example of using multiple signal levels to transmit two bits of digital data simultaneously on a single transmission medium between functional units.
"A 3.3V 128Mb Multilevel NAND Flash Memory for Mass Storage Application", Jung et al. Proceedings International Solid States Circuit Conference, 1996, paper TIP2.1, describes a flash memory cell that uses four separate voltage levels to retain two bits of data. The peripheral circuitry encodes the digital data to the appropriate voltage level for storage in the memory cell. The peripheral circuitry then senses the voltage level for the memory cell and determines the combination of logic state for the digital data.
"A 98 mm.sup.2 3.3V 64 Mb Flash Memory with FN-NOR Type 4 Level Cell", Ohkawa et al. Proceedings International Solid States Circuit Conference, 1996, paper TIP2.3, discloses a 64 Mb flash memory that also uses 4 voltage levels to store two bits of digital data.
"A 3.4 M byte/Sec. Programming 3-Level NAND Flash Memory Saving 40% Die Size Per Bit" Tanaka et al. Symposium of VLSI Circuits, Digest of Technical Papers, 1997, pp 65-66, has three threshold level corresponding to a 0, 1, and 2 thus allowing a pair of memory cells to store three bits of digital data.